Graphene is a promising material for microelectronic devices. A commonly proposed architecture for a gated graphene component is a graphitic layer containing graphene on a substrate, with metal contacts on the graphene and a channel region in the graphene between the contacts. This architecture suffers from lack of control over carrier density in the graphene in the channel region and under the contacts. Carrier density in the channel region may be modulated to operate the gated graphene component, while it is desirable to maintain a high carrier density under the contacts, in order to reduce the parasitic resistance of the device. Attaining independent control of the carrier density under the contacts in a structure that can be integrated into a microelectronic device with other components such as transistors has been challenging.